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high speed, isolated rs-485 transceiver with integrated transformer driver adm2485 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features half-duplex, isolated rs-485 transceiver integrated oscillator driver for external transformer profibus? compliant complies with ansi/tia/eia rs-485-a-98 and iso 8482:1987(e) data rate: 16 mbps 5 v or 3.3 v operation (v dd1 ) 50 nodes on bus high common-mode transient immunity: >25 kv/s isolated de out status output thermal shutdown protection safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 reinforced insulation, v iorm = 560 v peak operating temperature range: C40c to +85c wide-body, 16-lead soic package applications isolated rs-485/rs-422 interfaces profibus networks industrial field networks multipoint data transmission systems functional block diagram rts v dd1 de out gnd 1 a b v dd2 gnd 2 galvanic isolation d1 d2 txd rxd re adm2485 osc 06021-001 figure 1. general description the adm2485 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. it is designed for balanced transmission lines and complies with ansi/tia/eia rs-485-a-98 and iso 8482:1987(e). the device employs analog devices, inc., i coupler? technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. an on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power with an external transformer. the logic side of the device can be powered with either a 5 v or a 3.3 v supply, and the bus side is powered with an isolated 5 v supply. the adm2485 driver has an active high enable. the driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when v dd1 or v dd2 = 0 v. also provided is an active high receiver disable that causes the receive output to enter a high impedance state. the device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. the part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body soic package.
adm2485 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 package characteristics ............................................................... 6 regulatory information ............................................................... 6 insulation and safety-related specifications ............................ 6 vde 0884-2 insulation characteristics ..................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 test circ u its ..................................................................................... 13 circuit description ......................................................................... 14 electrical isolation ...................................................................... 14 tr uth tables ................................................................................. 14 thermal shutdown .................................................................... 14 receiver fail-safe inputs ........................................................... 14 magnetic field immunity .......................................................... 15 applications information .............................................................. 16 pcb layout ................................................................................. 16 transformer suppliers ............................................................... 16 applications diagram ................................................................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 12/07rev. 0 to rev. a updated format..................................................................universal changes to features section............................................................ 1 changes to table 4............................................................................ 6 changes to vde 0884-2 insulation characteristics section ...... 7 changes to pcb section and figure 34 ....................................... 16 updated outline dimensions ....................................................... 17 1/07revision 0: initial version
adm2485 rev. a | page 3 of 20 specifications 2.7 v v dd1 5.5 v, 4.75 v v dd2 5.25 v, t a = t min to t max , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments driver differential outputs differential output voltage, v od 5 v r = , see figure 21 2.1 5 v r = 50 (rs-422), see figure 21 2.1 5 v r = 27 (rs-485), see figure 21 2.1 5 v v tst = C7 v to +12 v, v dd1 4.75 v, see figure 22 |v od | for complementary output states 0.2 v r = 27 or 50 , see figure 21 common-mode output voltage, v oc 3 v r = 27 or 50 , see figure 21 |v oc | for complementary output states 0.2 v r = 27 or 50 , see figure 21 output short-circuit current, v out = high 60 200 ma ?7 v v out +12 v output short-circuit current, v out = low 60 200 ma ?7 v v out +12 v bus enable output output high voltage v dd2 ? 0.1 v i ode = 20 a v dd2 ? 0.3 v dd2 ? 0.1 v i ode = 1.6 ma v dd2 ? 0.4 v dd2 ? 0.2 v i ode = 4 ma output low voltage 0.1 v i ode = ?20 a 0.1 0.3 v i ode = ?1.6 ma 0.2 0.4 v i ode = ?4 ma logic inputs input high voltage 0.7 v dd1 v txd, rts, re input low voltage 0.25 v dd1 v txd, rts, re cmos logic input current (txd, rts, re ) ?10 +0.01 +10 a txd, rts, re = v dd1 or 0 v receiver differential inputs differential input threshold voltage, v th ?200 +200 mv ?7 v v cm +12v input hysteresis 70 mv ?7 v v cm +12v input resistance (a, b) 20 30 k ?7 v v cm +12v input current (a, b) 0.6 ma v in = +12 v ?0.35 ma v in = ?7 v rxd logic output output high voltage v dd1 ? 0.1 v i out = +20 a, v a ? v b = +0.2 v v dd1 ? 0.4 v dd1 ? 0.2 v i out = +1.5 ma, v a ? v b = +0.2 v output low voltage 0.1 v i out = ?20 a, v a ? v b = ?0.2 v 0.2 0.4 v i out = ?4 ma, v a ? v b = ?0.2 v output short-circuit current 7 85 ma v out = gnd or v cc tristate output leakage current 1 a 0.4 v v out 2.4 v transformer driver oscillator frequency 400 500 600 khz v dd1 = 5.5 v 230 330 430 khz v dd1 = 3.3 v switch-on resistance 0.5 1.5 start-up voltage 2.2 2.5 v
adm2485 rev. a | page 4 of 20 parameter min typ max unit test conditions/comments power supply current logic side 2.5 ma rts = 0 v, v dd1 = 5.5 v 2.3 ma 2.5 mbps, v dd1 = 5.5 v, see figure 23 5.0 6.5 ma 16 mbps, v dd1 = 5.5 v, see figure 23 1.26 ma rts = 0 v, v dd1 = 3.3 v 1.5 ma 2.5 mbps, v dd1 = 3.3 v, see figure 23 2.9 ma 16 mbps, v dd1 = 3.3 v, see figure 23 bus side 1.7 2.5 ma rts = 0 v 49.0 ma 2.5 mbps, rts = v dd1 , see figure 23 for load conditions 55.0 75.0 ma 16 mbps, rts = v dd1 , see figure 23 for load conditions common-mode transient immunity 1 25 kv/s transient magnitude = 800 v, v cm = 1 kv high frequency common-mode noise immunity 100 mv v hf = +5 v, ?2 v < v test2 < +7 v, 1 mhz < f test < 50 mhz, see figure 24 1 cm is the maximum common-mode voltage slew rate that can be sustained while maint aining specification-compliant operation. v cm is the common-mode potential difference between the logic and bus sides. the transient magnitude is the range over which the common mode is slewed. the comm on-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
adm2485 rev. a | page 5 of 20 timing specifications 2.7 v v dd1 5.5 v, 4.75 v v dd2 5.25 v, t a = t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments driver maximum data rate 16 mbps propagation delay input-to-output t plh , t phl 25 45 55 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 25 rts-to-de out propagation delay 20 35 55 ns see figure 26 driver output-to- output , t skew 2 5 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 2 and figure 25 rise/fall time, t r , t f 5 15 ns r ldiff = 54 , c l1 = c l2 = 100 pf, see figure 2 and figure 25 enable time 43 53 ns see figure 4 and figure 27 disable time 43 55 ns see figure 4 and figure 27 enable skew, |t azh ? t bzl |, |t azl ? t bzh | 1 3 ns see figure 4 and figure 27 disable skew, |t ahz ? t blz |, |t alz ? t bhz | 2 5 ns see figure 4 and figure 27 receiver propagation delay, t plh , t phl 25 45 55 ns c l = 15 pf, see figure 3 and figure 28 differential skew, t skew 5 ns c l = 15 pf, see figure 3 and figure 28 enable time 3 13 ns r l = 1 k, c l = 15 pf, see figure 5 and figure 29 disable time 3 13 ns r l = 1 k, c l = 15 pf, see figure 5 and figure 29 timing diagrams 06021-012 t phl t plh 3v 0v v out b a + v out 0v ? v out 1.5v 1.5v t f t r 10% point 10% point 90% point 90% point 1/2v out t skew = |t plh ? t phl | figure 2. driver propagation delay, rise/fall timing t skew = |t plh ? t phl | a ? b rxd 0v 0v 1.5v 1.5v t plh t phl v oh v ol 06021-013 figure 3. receiver propagation delay v oh v oh ? 0.5v v ol v oh + 0.5v t lz t zl t hz t zh a ? b a ? b rts 0.7v dd1 0.3v dd1 0.5v dd1 0.5v dd1 2.3v 2.3v 0v 06021-014 figure 4. driver enable/disable timing 0.7 v dd1 0.3v dd1 0.5v dd1 0.5v dd1 v oh v ol output low output high t lz t zl t hz t zh v oh ? 0.5v v oh + 0.5v 1.5v 1.5v rxd rxd re 0v 06021-015 figure 5. receiver enable/disable timing
adm2485 rev. a | page 6 of 20 package characteristics table 3. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 3 pf f = 1 mhz input capacitance 2 c i 4 pf input ic junction-to-case thermal resistance jci 33 c/w thermocouple located at center of package underside output ic junction-to-case thermal resistance jco 28 c/w thermocouple located at center of package underside 1 device considered a 2-terminal device: pin 1 to pin 8 are shorted together and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory information table 4. adm2485 approvals organization approval type notes ul recognized under the component recognition program of underwriters laboratories, inc. in accordance with ul 1577, each adm2485 is proof tested by applying an insulation test voltage 3000 v rms for 1 second (current leakage detection limit = 5 a). vde certified according to din v vde v 0884-10 (vde v 0884-10): 2006-12 in accordance with din v vde v 0884-10, each adm2485 is proof tested by applying an insulati on test voltage 1050 v peak for 1 second (partial discharge detection limit = 5 pc). insulation and safety-related specifications table 5. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (external clearance) l(i01) 5.15 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 5.5 min mm measured from input termin als to output terminals, shortest distance along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303-1 isolation group iiia material group (din vde 0110: 1989-01, table 1)
adm2485 rev. a | page 7 of 20 vde 0884-2 insulation characteristics this isolator is suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data must be ensured by means of protective circuits. an asterisk (*) on packages denotes din v vde v 0884-10 approval. table 6. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv 300 v rms i to iii 400 v rms i to ii climatic classification 40/85/21 pollution degree (din vde 0110: 1989-01, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage v pr method b1: v iorm 1.875 = v pr , 100% production tested, t m = 1 sec, partial discharge < 5 pc 1050 v peak method a (after environmental tests, subgroup 1): v iorm 1.6 = v pr , t m = 60 sec, partial discharge <5 pc 896 v peak method a (after input and/or safety test, subgroup 2/3): v iorm 1.2 = v pr , t m = 60 sec, partial discharge <5 pc 672 v peak highest allowable overvoltage 1 v tr 4000 v peak safety-limiting values 2 case temperature t s 150 c input current i s, input 265 ma output current i s, output 335 ma insulation resistance at t s 3 r s >10 9 1 transient overvoltage, t tr = 10 sec. 2 the safety-limiting value is the maximum value allowed in the ev ent of a failure. see figure 14 fo r the thermal derating curve . 3 v io = 500 v.
adm2485 rev. a | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. all voltages are relative to their respective grounds. table 7. parameter rating v dd1 ?0.5 v to +6 v v dd2 ?0.5 v to +6 v digital input voltage (rts, re , txd) ?0.5 v to v dd1 + 0.5 v digital output voltage rxd ?0.5 v to v dd1 + 0.5 v de out ?0.5 v to v dd2 + 0.5 v d1, d2 13 v driver output/receiver input voltage ?9 v to +14 v operating temperature range ?40c to +85c storage temperature range ?55c to +150c average output current per pin ?35 ma to +35 ma ja thermal impedance 73c/w lead temperature soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adm2485 rev. a | page 9 of 20 pin configuration and fu nction descriptions d1 1 d2 2 g nd 1 3 v dd1 4 v dd2 16 gnd 2 15 gnd 2 14 b 13 rxd 5 a 12 re 6 gnd 2 11 rts 7 de out 10 txd 8 gnd 2 9 adm2485 top view (not to scale) 06021-002 figure 6. pin configuration table 8. pin function description pin no. mnemonic function 1 d1 transformer driver terminal 1. 2 d2 transformer driver terminal 2. 3 gnd 1 ground, logic side. 4 v dd1 power supply, logic side (3.3 v or 5 v). decoupling capacitor to gnd 1 required; capacitor value should be between 0.01 f and 0.1 f. 5 rxd receiver output data. this output is high when (a ? b) > 200 mv and low when (a ? b) < ?200 mv. the output is tristated when the receiv er is disabled, that is, when re is driven high. 6 re receiver enable input. this is an active-low input. driving this input low enables the receiver; driving it high disables the receiver. 7 rts driver enable input. driving this input high en ables the driver; driving it low disables the driver. 8 txd driver input. data to be transmitted by the driver is appl ied to this input. 9, 11, 14, 15 gnd 2 ground, bus side. 10 de out driver enable status output. 12 a noninverting driver output/receiver inp ut. when the driver is disabled or v dd1 or v dd2 is powered down, pin a is put in a high impedance state to avoid overloading the bus. 13 b inverting driver output/receiver input. when the driver is disabled or v dd1 or v dd2 is powered down, pin b is put in a high impedance state to avoid overloading the bus. 16 v dd2 power supply, bus side (isolated 5 v supply). decoupling capacitor to gnd 2 required; capacitor value should be between 0.01 f and 0.1 f.
adm2485 rev. a | page 10 of 20 typical performance characteristics 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 ?40 ?20 0 20 40 60 80 supply current (ma) temperature (c) i dd1 _re_enable_v dd1 = 5.5v i dd2 _de_enable_v dd1 = 5.5v 06021-016 figure 7. unloaded supply current vs. temperature 5.0 4.0 3.0 2.0 1.0 0 4.5 3.5 2.5 1.5 0.5 ?40 ?20 0 20 40 60 80 i dd1 supply current (ma) temperature (c) i dd1 _profibus load_txd = 16mbps_v dd1 = 5.00v i dd1 _profibus load_txd = 2mbps_v dd1 = 5.00v i dd1 _no load_txd = 16mbps_v dd1 = 5.00v i dd1 _no load_txd = 2mbps_v dd1 = 5.00v 06021-017 figure 8. logic si de supply current (i dd1 = 1 ma) vs. temperature 60 40 50 30 20 10 0 ?40 ?20 0 20 40 60 80 i dd2 supply current (ma) temperature (c) i dd2 _ profibus load_txd = 16mbps_v dd2 = 5.00v i dd2 _no load_txd = 16mbps_v dd2 = 5.00v i dd2 _no load_txd = 2mbps_v dd2 = 5.00v i dd2 _profibus load_txd = 2mbps_v dd2 = 5.00v 06021-018 figure 9. bus side supply current (i dd2 = 2 ma) vs. temperature 60 40 50 30 20 10 0 ?40 ?20 0 20 40 60 80 driver propagation delay (ns) temperature (c) t plha t plhb t phla t phlb 06021-019 figure 10. driver propagation delay vs. temperature 60 40 50 30 20 10 0 ?40 ?20 0 20 40 60 80 receiver propagation delay (ns) temperature (c) rx prop delay, t plh _v dd2 = 5.00v rx prop delay, t phl _v dd2 = 5.00v 06021-020 figure 11. receiver propagation delay vs. temperature ch1 2.0v ? ch3 2.0v ? ch2 2.0v ? m20.0ns 1.25gs/s it 8.0ps/pt a ch3 2.60v 2 3 di b a 0 6021-021 figure 12. driver/receiver propagation delay, low to high (r ldiff = 54 , c l1 = c l2 = 100 pf)
adm2485 rev. a | page 11 of 20 ch1 1.0v ? ch3 2.0v ? ch2 1.0v ? m10.0ns a ch1 120mv 3 1 t 19.8000ns 06021-022 figure 13. driver/receiver propagation delay, high to low (r ldiff = 54 , c l1 = c l2 = 100 pf) case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side 1 side 2 06021-023 figure 14. thermal derating curve, dependence of safety-limiting values with case temperature per vde 0884-2 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 012345 output current (ma) output voltage (v) 06021-024 figure 15. output current vs. receiver output high voltage 60 50 40 30 20 10 0 012345 output current (ma) output voltage (v) 06021-025 figure 16. output current vs. receiver output low voltage 4.75 4.74 4.73 4.72 4.71 4.70 4.69 4.68 4.67 ?40 ?20 0 20 40 60 80 output voltage (v) temperature (c) 06021-031 figure 17. receiver output high voltage vs. temperature (i dd2 = C4 ma) 0.32 0.30 0.28 0.26 0.24 0.22 0.20 ?40 ?20 0 20 40 60 80 output voltage (v) temperature (c) 06021-032 figure 18. receiver output low voltage vs. temperature (i dd2 = C4 ma)
adm2485 rev. a | page 12 of 20 ch1 2.0v ? ch2 2.0v ? m400ns 125ms/s 8.0ns/pt a ch2 1.52v 2 1 d1 d2 06021-033 figure 19. switching waveforms (50 pull-up to v dd1 on d1 and d2) ch1 2.0v ? ch2 2.0v ? m80ns 625ms/s 1.6ns/pt a ch2 1.52v 1 d1 d2 06021-034 figure 20. switching waveforms (break-before-make, 50 pull-up to v dd1 on d1 and d2)
adm2485 rev. a | page 13 of 20 test circuits v oc r r v od 06021-003 figure 21. driver voltage measurement 60 ? v od3 375 ? 375 ? v test 06021-004 figure 22. driver voltage measurement v dd1 de out 150 ? gnd 1 a b v dd2 gnd 2 galvanic isolation v dd2 195? 110? 195? gnd 2 rts txd rxd re 06021-005 figure 23. supply-current measurement test circuit 06021-006 v dd1 de out gnd 1 b a galvanic isolation 50? 110nf 50? v test2 rts txd rxd gnd 2 2.2k ? v dd2 gnd 2 100nf 100nf v cm (hf) 470nf 22k ? f test , v hf re 195 ? 110 ? 195 ? v dd2 gnd 2 figure 24. high frequency, common-mode noise test circuit c l1 r ldiff a b c l2 0 6021-007 figure 25. driver propagation delay v dd1 de out gnd 1 a b v dd2 gnd 2 galvanic isolation rts txd rxd re 150 ? 50pf 06021-008 figure 26. rts to de out propagation delay v cc s2 v out 110 ? 50pf s1 b a txd rts 0 6021-009 figure 27. driver enable/disable c l v out re a b 06021-010 figure 28. receiver propagation delay v cc s2 v out r l c l +1.5 v ?1.5v s1 re re in 06021-011 figure 29. receiver enable/disable
adm2485 rev. a | page 14 of 20 circuit description electrical isolation in the adm2485, electrical isolation is implemented on the logic side of the interface. therefore, the part has two main sections: a digital isolation section and a transceiver section (see figure 30 ). driver input and data enable, applied to the txd and rts pins, respectively, and referenced to logic ground (gnd 1 ), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (gnd 2 ). similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the rxd pin referenced to logic ground. icoupler technology the digital signals are transmitted across the isolation barrier using i coupler technology. this technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. at the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. isolation barrier v dd2 v dd1 a b de out gnd 2 gnd 1 txd rts rxd re encode decode decode decode encode encode d r transceiver digital isolation d1 d2 osc 06021-026 figure 30. adm2485 digital isolation and transceiver sections truth tables table 10 and table 11 use the abbreviations found in table 9 . table 9. truth table abbreviations letter description h high level i indeterminate l low level x irrelevant z high impedance (off ) nc disconnected table 10. transmitting supply status inputs outputs v dd1 v dd2 rts txd a b de out on on h h h l h on on h l l h h on on l x z z l on off x x z z l off on x x z z l off off x x z z l table 11. receiving supply status input outputs v dd1 v dd2 a ? b re rxd on on >+0.2 v l or nc h on on adm2485 rev. a | page 15 of 20 magnetic field immunity because i couplers use a coreless technology, no magnetic components are present and the problem of magnetic saturation of the core material does not exist. therefore, i couplers have essentially infinite dc field immunity. the following analysis defines the conditions under which this can occur. the adm2485 3.3 v operating condition is examined because it represents the most susceptible mode of operation. the limitation on the i coupler ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil, in this case) is made sufficiently large, either to falsely set or reset the decoder. the voltage induced across the bottom coil is given by ? ? ? ? ? ? ? = 2 n r dt d v ; n = 1, 2 n (1) where, if the pulses at the transformer output are greater than 1.0 v in amplitude: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of n th turn in the receiving coil (cm). the decoder has a sensing threshold of about 0.5 v; therefore, there is a 0.5 v margin where induced voltages can be tolerated. given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 31 . magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m 100 10 1 0.1 0.01 0.001 maximum allowable magnetic flux density (kgauss) 0 6021-027 figure 31. maximum allowable external magnetic flux density vs. magnetic field frequency for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil, which is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse and it is the worst-case polarity, it reduces the received pulse from >1.0 v to 0.75 v, still well above the 0.5 v sensing threshold of the decoder. figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances from the adm2485 transformers. magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m distance = 1m distance = 100mm distance = 5mm 1000 100 0.1 0 10 0.01 maximum allowable current (ka) 06021-028 figure 32. maximum allowable current for various current-to-adm2485 spacings at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board (pcb) traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care must be taken in the layout of such traces to avoid this possibility.
adm2485 rev. a | page 16 of 20 applications information pcb layout the adm2485 isolated rs-485 transceiver requires no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 33 ). bypass capacitors are most conveniently connected between pin 3 and pin 4 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value must be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. bypassing between pin 9 and pin 16 is also recommended unless the ground wires on the v dd2 side are connected close to the package. d1 d2 gnd 1 v dd1 rxd re rts txd v dd2 gnd 2 gnd 2 b a gnd 2 de out gnd 2 adm2485 0 6021-029 figure 33. recommended printed circuit board layout in applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the device absolute maximum ratings, thereby leading to latch-up or permanent damage. transformer suppliers the transformer primarily used with the adm2485 must be a center-tapped transformer winding. the turns ratio of the transformer must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum input voltage. table 1 2 shows adm2485 transformer suppliers. table 12. transformer suppliers manufacturer primary voltage 3.3 v primary voltage 5 v coilcraft da2304-al da2303-al c&d technologies 782485/35c 782485/55c applications diagram the adm2485 integrates a transformer driver that, when used with an external transformer and ldo, generates an isolated 5 v power supply, to be supplied between v dd2 and gnd 2 . d1 and d2 of the adm2485 drive the center-tapped transformer t1. a pair of schottky diodes and a smoothing capacitor is used to create a rectified signal from the secondary winding. the adp3330 linear voltage regulator provides a regulated 5 v power supply to the adm2485 bus-side circuitry (v dd2 ), as shown in figure 34 . when the adm2485 is powered by 3.3 v on the logic side, a 1ct:2.2ct transformer t1 is required to step up the 3.3 v to 6 v, ensuring enough headroom for the adp3330 ldo to output a regulated 5 v output. if adm2485 is powered by 5 v on the logic side, a 1ct:1.5ct transformer t1 is required, ensuring enough headroom for the adp3330 ldo to output a regulated 5 v output. 06021-030 v cc v cc iso 5v adp3330 in 10f 100nf out 5v sd 1n5817 1n5817 v dd1 d1 d2 v dd2 gnd 2 adm2485 gnd err nr 22f 10f mlc t1 isolation barrier 100nf gnd 1 figure 34. applications diagram
adm2485 rev. a | page 17 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 35. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model data rate (mbps) temperature rang e package description package option adm2485brwz 1 16 ?40c to +85c 16-lead soic_w rw-16 ADM2485BRWZ-REEL7 1 16 ?40c to +85c 16-lead soic_w rw-16 1 z = rohs compliant part.
adm2485 rev. a | page 18 of 20 notes
adm2485 rev. a | page 19 of 20 notes
adm2485 rev. a | page 20 of 20 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06021-0-12/07(a)

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